The present invention relates to equipment for testing of integrated circuits. More particularly, the present invention relates to a method and apparatus for producing substantially co-planar bonding pads for mounting probes to a substrate for wafer testing of semiconductor integrated circuits.
In semiconductor integrated circuit manufacturing, it is conventional to test the integrated circuits (“ICs”) during manufacturing and prior to shipment to ensure proper operation. Wafer testing is a well-known testing technique commonly used in production testing of wafer-mounted semiconductor ICs, wherein a temporary electrical current is established between test equipment (e.g., automatic test equipment otherwise known as ATE) and each IC mounted on the wafer to demonstrate proper performance of the ICs. Exemplary components used in wafer testing include an ATE test board and a probe card. An exemplary ATE test board is a multilayer printed circuit board that is connected to the ATE, and that transfers the test signals back and forth between the ATE and a probe card. An exemplary probe card is a printed circuit board that generally contains several hundred probe needles positioned to establish electrical contact with a series of connection terminals on the IC wafer.
Known probe cards include probe cards available from Kulicke & Soffa, Inc. of Willow Grove, Pa. One such probe card comprises a printed circuit board, a probe head having a plurality of flexible probes, and a space transformer which electrically connects the probes to the printed circuit board. For example, the space transformer may comprise a multi-layer ceramic substrate or a multi-layer organic substrate.
It is also known to mount each of a plurality of flexible probes to a mounting surface of the space transformer. Typically, the probes are mounted to electrically conductive, preferably metallic bonding pads or circuit traces formed on (or integrated as part of) the substrate through conventional plating or etching techniques well known to those of ordinary skill in the art of semiconductor fabrication.
One difficulty in the fabrication of probe cards is that the mounting surface of the space transformer (as well as the entire substrate) is subject to waviness or non-planarity, with a result that the mounting surface for the probes is not flat. Mounting of probes to a non-planar surface leads to undesirable variation in the positions of the probe tips, which connect with the IC connection terminals. Tight positional tolerances of all the probe tips within the probe assembly are desirable for establishing and maintaining identical contacting conditions between the individual probe tips and the terminals of the tested chips. Positional tolerances affect both the position of the probe tips relative to the corresponding terminals and the force required to establish a satisfactory electrical connection between the probes and the IC connection terminals. When probe tips are of a probe card are substantially non-planar with respect to one another probing of the integrated circuits during testing may require overtravel in order to ensure contact between all of the probes and the corresponding terminals on the integrated circuit(s) to be tested. Such overtravel may reduce the life of the probes, and may also increase contact resistance between the probe tips and the corresponding terminals on the integrated circuit(s) to be tested.
During wafer testing, an array of test probe tips is brought into contact with an array of semiconductor pads/terminals in order to apply and sense voltages in an effort to ascertain the quality of the manufactured semiconductor devices. The surface of the wafer is typically maintained extraordinarily flat due to the process of optical lithography and the demands of the dimensional precision utilized to manufacture sub-micron line widths. The silicon wafers are typically polished extremely flat and during processing, planarization methods are frequently employed to maintain the flatness. Manufacturing methods utilized for ceramic or organic substrates are not typically made to the precision tolerances utilized for wafer manufacturing. The different materials employed in the substrate (e.g., metals, dielectrics), the methods applied (multilayer ceramics, plating), and their individual thickness (which are typically much larger than the metal and dielectric thin films on the surface of a semiconductor die) all contribute to the overall non-planarity.
The final steps in the preparation of the substrates normally involve plating (e.g., nickel and gold) on the surfaces of the traces (e.g., copper traces) that typically comprise the top layers of the substrate. Although electroplating can produce very smooth surface features, the underlying features of the vias and their means of manufacture may create one source of the non-planarity of the pads. The thermal expansion rates, internal stresses and the temperatures employed in the processing of the bulk of the substrates are another source of non-planarity. In order to tightly control positional tolerances of the probe tips, it is desirable that the mounting surface of the plurality of probes be as nearly flat or planar as is practicable.